2014.01.10
SEU Mitigation for Stratix V Devices
9
SV51011
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This chapter describes the error detection features in Stratix V devices. You can use these features to mitigate
single event upset (SEU) or soft errors.
Related Information
Lists the planned updates to the Stratix V Device Handbook chapters.
Error Detection Features
The on-chip error detection CRC circuitry allows you to perform the following operations without any
impact on the fitting or performance of the device:
? Auto-detection of CRC errors during configuration.
? Optional CRC error detection and identification in user mode.
? Optional internal scrubbing in user mode. When enabled, this feature corrects single-bit and double-
adjacent errors automatically.
? Testing of error detection functions by deliberately injecting errors through the JTAG interface.
Configuration Error Detection
When the Quartus II software generates the configuration bitstream, the software also computes a 16-bit
CRC value for each frame. A configuration bitstream can contain more than one CRC values depending on
the number of data frames in the bitstream. The length of the data frame varies for each device.
When a data frame is loaded into the FPGA during configuration, the precomputed CRC value shifts into
the CRC circuitry. At the same time, the CRC engine in the FPGA computes the CRC value for the data
frame and compares it against the precomputed CRC value. If both CRC values do not match, the nSTATUS
pin is set to low to indicate a configuration error.
You can test the capability of this feature by modifying the configuration bitstream or intentionally corrupting
the bitstream during configuration.
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相关PDF资料
DK-DSP-2S180N DSP PRO KIT W/SII EP2S180N
DK-DSP-3C120N KIT DEV DSP CYCLONE III EDITION
DK-K7-CONN-CES-G KINTEX-7 FPGA CONNECTIVITY KIT
DK-K7-EMBD-CES-G-J KINTEX-7 FPGA EMBEDDED KIT JAPAN
DK-MAXII-1270N KIT DEV MAXII W/EPM 1270N
DK-N2EVAL-3C25N KIT DEV NIOS II CYCLONE III ED.
DK-NIOS-2C35N NIOS II KIT W/CYCLONE II EP2C35N
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